Publications
2020 |
Thierry Simon Lejla Batina, Joan Daemen Vincent Grosso Pedro Maat Costa Massolino Kostas Papagiannopoulos Francesco Regazzoni Niels Samwel Friet: an authenticated encryption scheme with built in fault detection Conference Eurocrypt 2020, 2020. @conference{Simon2020, title = {Friet: an authenticated encryption scheme with built in fault detection}, author = {Thierry Simon, Lejla Batina, Joan Daemen, Vincent Grosso, Pedro Maat Costa Massolino, Kostas Papagiannopoulos, Francesco Regazzoni, Niels Samwel}, year = {2020}, date = {2020-03-31}, booktitle = {Eurocrypt 2020}, keywords = {}, pubstate = {published}, tppubtype = {conference} } |
de la Alberto Ortiz RafaelZamacola, Alfonso Rodríguez Andrés Otero Eduardo Torre Automated Toolchain for Enhanced Productivity in Reconfigurable Multi-Accelerator Systems Conference 16th International Symposium on Applied Reconfigurable Computing, 2020. @conference{Ortiz2020, title = {Automated Toolchain for Enhanced Productivity in Reconfigurable Multi-Accelerator Systems}, author = {Alberto Ortiz, RafaelZamacola, Alfonso Rodríguez, Andrés Otero, Eduardo de la Torre}, year = {2020}, date = {2020-03-19}, booktitle = {16th International Symposium on Applied Reconfigurable Computing}, keywords = {}, pubstate = {published}, tppubtype = {conference} } |
Ognjen Glamocanin Louis Coulon, Francesco Regazzoni Mirjana Stojilovic Built-in self-evaluation of first order power side channel leakage for FPGA Conference 28th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020. @conference{Glamocanin2020, title = {Built-in self-evaluation of first order power side channel leakage for FPGA}, author = {Ognjen Glamocanin,Louis Coulon, Francesco Regazzoni, Mirjana Stojilovic}, year = {2020}, date = {2020-02-14}, booktitle = {28th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays}, keywords = {}, pubstate = {published}, tppubtype = {conference} } |
2019 |
Vuotto, Simone; Narizzano, Massimo; Pulina, Luca; Tacchella, Armando Poster: Automatic Consistency Checking of Requirements with ReqV Conference 2019 IEEE International Conference on Software Testing, Verification and Validation Workshops (ICSTW), 2019. @conference{Vuotto2019, title = {Poster: Automatic Consistency Checking of Requirements with ReqV}, author = {Simone Vuotto and Massimo Narizzano and Luca Pulina and Armando Tacchella}, year = {2019}, date = {2019-12-31}, booktitle = {2019 IEEE International Conference on Software Testing, Verification and Validation Workshops (ICSTW)}, keywords = {}, pubstate = {published}, tppubtype = {conference} } |
Vuotto, Simone; Narizzano, Massimo; Pulina, Luca; Tacchella, Armando Automata Based Test Generation with SpecPro Conference 2019 IEEE/ACM International Workshop on Requirements Engineering and Testing (RET), 2019. @conference{vuotto2019specpro, title = {Automata Based Test Generation with SpecPro}, author = {Simone Vuotto and Massimo Narizzano and Luca Pulina and Armando Tacchella}, year = {2019}, date = {2019-12-31}, booktitle = {2019 IEEE/ACM International Workshop on Requirements Engineering and Testing (RET)}, keywords = {}, pubstate = {published}, tppubtype = {conference} } |
Fanni Tiziana; Madronal, Daniel; Rubattu Claudio; Sau Carlo; Palumbo Francesca; Juarez Eduardo; Pelcat Maxime; Sanz Cesar; Raffo Luigi Run-time Performance Monitoring of Heterogenous Hw/Sw Platforms Using PAPI Conference VDE VERLAG, 2019, ISBN: 978-3-8007-5045-0. @conference{fanniCF_2019, title = {Run-time Performance Monitoring of Heterogenous Hw/Sw Platforms Using PAPI}, author = {Fanni, Tiziana; Madronal, Daniel; Rubattu, Claudio; Sau, Carlo; Palumbo, Francesca; Juarez, Eduardo; Pelcat, Maxime; Sanz, Cesar; Raffo, Luigi}, editor = {FSP Workshop 2019; Sixth International Workshop on FPGAs for Software Programmers}, url = {https://ieeexplore.ieee.org/document/8891817}, isbn = {978-3-8007-5045-0}, year = {2019}, date = {2019-12-12}, publisher = {VDE VERLAG}, keywords = {}, pubstate = {published}, tppubtype = {conference} } |
Bit-Monnot, Arthur; Leofante, Francesco; Pulina, Luca; Abraham, Erika; Tacchella, Armando SMT-based Planning for Robots in Smart Factories Conference Proceedings of IEA-AIE 2019, 2019. @conference{Bit-Monnot2018, title = {SMT-based Planning for Robots in Smart Factories}, author = {Arthur Bit-Monnot and Francesco Leofante and Luca Pulina and Erika Abraham and Armando Tacchella}, url = {https://arxiv.org/pdf/1806.07135}, year = {2019}, date = {2019-07-10}, booktitle = {Proceedings of IEA-AIE 2019}, abstract = {Smart factories are on the verge of becoming the new industrial paradigm, wherein optimization permeates all aspects of production, from concept generation to sales. To fully pursue this paradigm, flexibility in the production means as well as in their timely organization is of paramount importance. AI is planning a major role in this transition, but the scenarios encountered in practice might be challenging for current tools. Task planning is one example where AI enables more efficient and flexible operation through an online automated adaptation and rescheduling of the activities to cope with new operational constraints and demands. In this paper we present SMarTplan, a task planner specifically conceived to deal with real-world scenarios in the emerging smart factory paradigm. Including both special-purpose and general-purpose algorithms, SMarTplan is based on current automated reasoning technology and it is designed to tackle complex application domains. In particular, we show its effectiveness on a logistic scenario, by comparing its specialized version with the general purpose one, and extending the comparison to other state-of-the-art task planners. }, keywords = {}, pubstate = {published}, tppubtype = {conference} } Smart factories are on the verge of becoming the new industrial paradigm, wherein optimization permeates all aspects of production, from concept generation to sales. To fully pursue this paradigm, flexibility in the production means as well as in their timely organization is of paramount importance. AI is planning a major role in this transition, but the scenarios encountered in practice might be challenging for current tools. Task planning is one example where AI enables more efficient and flexible operation through an online automated adaptation and rescheduling of the activities to cope with new operational constraints and demands. In this paper we present SMarTplan, a task planner specifically conceived to deal with real-world scenarios in the emerging smart factory paradigm. Including both special-purpose and general-purpose algorithms, SMarTplan is based on current automated reasoning technology and it is designed to tackle complex application domains. In particular, we show its effectiveness on a logistic scenario, by comparing its specialized version with the general purpose one, and extending the comparison to other state-of-the-art task planners. |
Bit-Monnot Arthur; Pulina, Luca; Tacchella Armando Cyber-Physical Planning: Deliberation for Hybrid Systems with a Continuous Numeric State Conference Proceedings of ICAPS 2019, 2019. @conference{Bit-Monnot2019, title = {Cyber-Physical Planning: Deliberation for Hybrid Systems with a Continuous Numeric State}, author = {Bit-Monnot, Arthur; Pulina, Luca; Tacchella, Armando}, year = {2019}, date = {2019-05-31}, booktitle = {Proceedings of ICAPS 2019}, abstract = {Cyber-physical systems pose unique deliberation challenges, where complex strategies must be autonomously derived and executed in the physical world, relying on continuous state representations and subject to safety and security constraints. Robots are a typical example of cyber-physical system where high-level decisions must be reconciled with motion-level de- cisions in order to provide guarantees on the validity and ef- ficiency of the plan. In this work we propose techniques to refine a high-level plan into a continuous state trajectory. The refinement is done by translating a high-level plan into a nonlinear optimization problem with constraints that can encode the intrinsic limita- tions and dynamics of the system as well as the rules for its continuous control. The refinement process either succeeds or yields an explanation that we exploit to refine the search space of a high-level task planner. We evaluate our approach on existing PDDL+ benchmarks as well as on a more realistic and challenging rover navigation problem. }, keywords = {}, pubstate = {published}, tppubtype = {conference} } Cyber-physical systems pose unique deliberation challenges, where complex strategies must be autonomously derived and executed in the physical world, relying on continuous state representations and subject to safety and security constraints. Robots are a typical example of cyber-physical system where high-level decisions must be reconciled with motion-level de- cisions in order to provide guarantees on the validity and ef- ficiency of the plan. In this work we propose techniques to refine a high-level plan into a continuous state trajectory. The refinement is done by translating a high-level plan into a nonlinear optimization problem with constraints that can encode the intrinsic limita- tions and dynamics of the system as well as the rules for its continuous control. The refinement process either succeeds or yields an explanation that we exploit to refine the search space of a high-level task planner. We evaluate our approach on existing PDDL+ benchmarks as well as on a more realistic and challenging rover navigation problem. |
Zamacola, Rafael; Martínez, Alberto García; Mora, Javier; Otero, Andrés; de Torre, Eduardo La Automated Tool and Runtime Support for Fine-Grain Reconfiguration in Highly Flexible Reconfigurable Systems Conference Proceedings of FCCM 2019, 2019. @conference{Zamacola2019, title = {Automated Tool and Runtime Support for Fine-Grain Reconfiguration in Highly Flexible Reconfigurable Systems}, author = {Rafael Zamacola and Alberto García Martínez and Javier Mora and Andrés Otero and Eduardo de La Torre}, year = {2019}, date = {2019-04-25}, booktitle = {Proceedings of FCCM 2019}, abstract = {Dynamic partial reconfiguration significantly reduces reconfiguration times when offloading a partial design. However, there are occasions when fine-tuning a circuit would greatly benefit from quicker reconfiguration times. To that end, authors present an automated tool and runtime support to reconfigure LUT-based multiplexers and constants. This approach has the benefit of faster reconfiguration times comparing with traditional reconfiguration flows. In contrast to conventional multiplexers and constants, it is possible to modify every part of the FPGA without the need to have a direct communication with the static system thus reducing reconfigurable interfaces and enabling the communication with reconfigurable modules surrounded by other reconfigurable modules. }, keywords = {}, pubstate = {published}, tppubtype = {conference} } Dynamic partial reconfiguration significantly reduces reconfiguration times when offloading a partial design. However, there are occasions when fine-tuning a circuit would greatly benefit from quicker reconfiguration times. To that end, authors present an automated tool and runtime support to reconfigure LUT-based multiplexers and constants. This approach has the benefit of faster reconfiguration times comparing with traditional reconfiguration flows. In contrast to conventional multiplexers and constants, it is possible to modify every part of the FPGA without the need to have a direct communication with the static system thus reducing reconfigurable interfaces and enabling the communication with reconfigurable modules surrounded by other reconfigurable modules. |
de la Suriano Florian Arrestier, Alfonso Rodriguez Julien Heulot Karol Desnos Maxime Pelcat Eduardo Torre DAMHSE: Programming heterogeneous MPSoCs with hardware acceleration using dataflow-based design space exploration and automated rapid prototyping Journal Article Microprocessors and Microsystems, 2019. @article{eonardoSuriano2019, title = {DAMHSE: Programming heterogeneous MPSoCs with hardware acceleration using dataflow-based design space exploration and automated rapid prototyping}, author = {eonardo Suriano, Florian Arrestier, Alfonso Rodriguez, Julien Heulot, Karol Desnos, Maxime Pelcat, Eduardo de la Torre}, year = {2019}, date = {2019-03-25}, journal = {Microprocessors and Microsystems}, keywords = {}, pubstate = {published}, tppubtype = {article} } |
Raquel Lazcano Daniel Madroñal, Eduardo Juarez Philippe Clauss Runtime Multi-versioning and Specialization inside a Memoized Speculative Loop Optimizer Conference International Conference on CompilerConstruction 2020, 2019. @conference{Lazcano2019, title = {Runtime Multi-versioning and Specialization inside a Memoized Speculative Loop Optimizer}, author = {Raquel Lazcano, Daniel Madroñal, Eduardo Juarez, Philippe Clauss}, year = {2019}, date = {2019-03-24}, booktitle = {International Conference on CompilerConstruction 2020}, keywords = {}, pubstate = {published}, tppubtype = {conference} } |
Vuotto, Simone Automata-Based Generation of Test Cases for Reactive Systems Conference Cyber-Physical systems PhD and Post-doc workshop, 2019. @conference{Vuotto2019b, title = {Automata-Based Generation of Test Cases for Reactive Systems}, author = {Simone Vuotto}, url = { http://ceur-ws.org/Vol-2457/10.pdf }, year = {2019}, date = {2019-03-23}, booktitle = {Cyber-Physical systems PhD and Post-doc workshop}, keywords = {}, pubstate = {published}, tppubtype = {conference} } |
Saman Payvar Jani Boutellier, Antoine Morvan Claudio Rubattu ; Pelcat, Maxime Extending Architecture Modeling for Signal Processing towards GPUs Conference IEEE Xplore Digital Library, 2019. @conference{Payvar2019, title = {Extending Architecture Modeling for Signal Processing towards GPUs}, author = {Saman Payvar, Jani Boutellier, Antoine Morvan, Claudio Rubattu, and Maxime Pelcat}, year = {2019}, date = {2019-03-20}, booktitle = {IEEE Xplore Digital Library}, keywords = {}, pubstate = {published}, tppubtype = {conference} } |
Sujit Rokka Chhetri Anomadarshi Barua, Sina Faezi Francesco Regazzoni Arquimedes Canedo ; Faruque, Mohammad Abdullah Al Tool of Spies: leaking your Ipby altering the 3D printer compiler Journal Article Forthcoming IEEE Transactions on Dependable and Secure Computing, Forthcoming. @article{Chhetri2019, title = {Tool of Spies: leaking your Ipby altering the 3D printer compiler}, author = {Sujit Rokka Chhetri, Anomadarshi Barua, Sina Faezi, Francesco Regazzoni, Arquimedes Canedo, and Mohammad Abdullah Al Faruque}, year = {2019}, date = {2019-03-15}, journal = {IEEE Transactions on Dependable and Secure Computing}, keywords = {}, pubstate = {forthcoming}, tppubtype = {article} } |
Honorat Alexandre; Desnos, Karol; Pelcat Maxime; Nezan Jean-François Modeling Nested For Loops with Explicit Parallelism in Synchronous Dataflow Graphs Conference Lecture Notes in Computer Science book series (LNCS, volume 11733), 2019. @conference{Honorat2019, title = {Modeling Nested For Loops with Explicit Parallelism in Synchronous Dataflow Graphs}, author = {Honorat, Alexandre; Desnos, Karol; Pelcat, Maxime; Nezan, Jean-François}, year = {2019}, date = {2019-03-14}, booktitle = {Lecture Notes in Computer Science book series (LNCS, volume 11733)}, keywords = {}, pubstate = {published}, tppubtype = {conference} } |
de la Luca Fanni Leonardo Suriano, Claudio Rubattu Pablo Sanchez Eduardo Torre ; Palumbo, Francesca A Dataflow Implementation of Inverse Kinematics on Reconfigurable Heterogeneous MPSoC Conference Proceedings of the Cyber-Physical Systems PhD Workshop 2019, 2019. @conference{Fanni2019, title = {A Dataflow Implementation of Inverse Kinematics on Reconfigurable Heterogeneous MPSoC}, author = {Luca Fanni, Leonardo Suriano, Claudio Rubattu, Pablo Sanchez, Eduardo de la Torre and Francesca Palumbo}, year = {2019}, date = {2019-03-13}, booktitle = {Proceedings of the Cyber-Physical Systems PhD Workshop 2019}, keywords = {}, pubstate = {published}, tppubtype = {conference} } |
Madroñal, Daniel; Fanni, Tiziana Run-time Performance Monitoring of Hardware Accelerators: POSTER Conference 16th ACM International Conference on Computing Frontiers, 2019. @conference{Madroñal2019, title = {Run-time Performance Monitoring of Hardware Accelerators: POSTER}, author = {Daniel Madroñal and Tiziana Fanni}, year = {2019}, date = {2019-03-07}, booktitle = {16th ACM International Conference on Computing Frontiers}, keywords = {}, pubstate = {published}, tppubtype = {conference} } |
Desnos, Karol; Palumbo, Francesca Dataflow Modeling for Reconfigurable Signal Processing Systems Book Chapter Handbook of Signal Processing Systems, 3rd Edition, 2019. @inbook{Desnos2019, title = {Dataflow Modeling for Reconfigurable Signal Processing Systems}, author = {Karol Desnos and Francesca Palumbo}, year = {2019}, date = {2019-03-07}, publisher = {Handbook of Signal Processing Systems, 3rd Edition}, keywords = {}, pubstate = {published}, tppubtype = {inbook} } |
Masin, Michael ; Palumbo, Francesca ; Adriaanse, J; Myrhaug, Hans ; Regazzoni, Francesco ; Sanchez, M; Zedda, Katiuscia Elicitation of Technical Requirements in Large Research Projects: the CERBERO approach Conference 34th ACM/SIGAPP Symposium On Applied Computing, 2019. @conference{Masin2019, title = {Elicitation of Technical Requirements in Large Research Projects: the CERBERO approach}, author = {Masin, Michael and Palumbo, Francesca and Adriaanse, J and Myrhaug, Hans and Regazzoni, Francesco and Sanchez, M and Zedda, Katiuscia}, year = {2019}, date = {2019-03-07}, booktitle = {34th ACM/SIGAPP Symposium On Applied Computing}, keywords = {}, pubstate = {published}, tppubtype = {conference} } |
Li, Lin; Sau, Carlo; Fanni, Tiziana; Li, Jingui; Viitanen, Timo; Christophec, Francois; Palumbo, Francesca; Raffo, Luigi; Huttunen, Heikki; Takala, Jarmo; Bhattacharyya, Shuvra S An Integrated Hardware/Software Design Methodology for Signal Processing Systems Journal Article Forthcoming Journal of Systems Architecture, Forthcoming. @article{Li2019, title = {An Integrated Hardware/Software Design Methodology for Signal Processing Systems}, author = {Lin Li and Carlo Sau and Tiziana Fanni and Jingui Li and Timo Viitanen and Francois Christophec and Francesca Palumbo and Luigi Raffo and Heikki Huttunen and Jarmo Takala and Shuvra S. Bhattacharyya}, doi = {10.1016/j.sysarc.2018.12.010}, year = {2019}, date = {2019-01-05}, journal = {Journal of Systems Architecture}, keywords = {}, pubstate = {forthcoming}, tppubtype = {article} } |
Madroñal, Daniel; Fanni, Tiziana Run-time Performance Monitoring of Hardware Accelerators: POSTER Inproceedings Proceedings of the 16th ACM International Conference on Computing Frontiers, pp. 289–291, ACM, Alghero, Italy, 2019, ISBN: 978-1-4503-6685-4. @inproceedings{Madronal:2019:RPM:3310273.3323423, title = {Run-time Performance Monitoring of Hardware Accelerators: POSTER}, author = {Daniel Madroñal and Tiziana Fanni}, url = {http://doi.acm.org/10.1145/3310273.3323423}, doi = {10.1145/3310273.3323423}, isbn = {978-1-4503-6685-4}, year = {2019}, date = {2019-01-01}, booktitle = {Proceedings of the 16th ACM International Conference on Computing Frontiers}, pages = {289--291}, publisher = {ACM}, address = {Alghero, Italy}, series = {CF '19}, keywords = {}, pubstate = {published}, tppubtype = {inproceedings} } |
Palumbo, Francesca; Fanni, Tiziana; Sau, Carlo; Pulina, Luca; Raffo, Luigi; Masin, Michael; Shindin, Evgeny; de Rojas, Pablo Sanchez; Desnos, Karol; Pelcat, Maxime; Rodríguez, Alfonso; Juárez, Eduardo; Regazzoni, Francesco; Meloni, Giuseppe; Zedda, Katiuscia; Myrhaug, Hans; Kaliciak, Leszek; Andriaanse, Joost; de Filho, Julio Olivieria; Muñoz, Pablo; Toffetti, Antonella Proceedings of the 16th ACM International Conference on Computing Frontiers, pp. 320–325, ACM, Alghero, Italy, 2019, ISBN: 978-1-4503-6685-4. @inproceedings{Palumbo:2019:CCM:3310273.3323436, title = {CERBERO: Cross-layer modEl-based fRamework for multi-oBjective dEsign of Reconfigurable Systems in unceRtain hybRid envirOnments: Invited Paper: CERBERO Teams from UniSS, UniCA, IBM Research, TASE, INSA-Rennes, UPM, USI, Abinsula, AmbieSense, TNO, S&T, CRF}, author = {Francesca Palumbo and Tiziana Fanni and Carlo Sau and Luca Pulina and Luigi Raffo and Michael Masin and Evgeny Shindin and Pablo Sanchez de Rojas and Karol Desnos and Maxime Pelcat and Alfonso Rodríguez and Eduardo Juárez and Francesco Regazzoni and Giuseppe Meloni and Katiuscia Zedda and Hans Myrhaug and Leszek Kaliciak and Joost Andriaanse and Julio de Olivieria Filho and Pablo Muñoz and Antonella Toffetti}, url = {http://doi.acm.org/10.1145/3310273.3323436}, doi = {10.1145/3310273.3323436}, isbn = {978-1-4503-6685-4}, year = {2019}, date = {2019-01-01}, booktitle = {Proceedings of the 16th ACM International Conference on Computing Frontiers}, pages = {320--325}, publisher = {ACM}, address = {Alghero, Italy}, series = {CF '19}, keywords = {}, pubstate = {published}, tppubtype = {inproceedings} } |
Madroñal, D; Arrestier, F; Sancho, J; Morvan, A; Lazcano, R; Desnos, K; Salvador, R; Menard, D; Juarez, E; Sanz, C PAPIFY: Automatic Instrumentation and Monitoring of Dynamic Dataflow Applications Based on PAPI Journal Article IEEE Access, 7 , pp. 111801-111812, 2019, ISSN: 2169-3536. @article{madronal_access_2019, title = {PAPIFY: Automatic Instrumentation and Monitoring of Dynamic Dataflow Applications Based on PAPI}, author = {D Madroñal and F Arrestier and J Sancho and A Morvan and R Lazcano and K Desnos and R Salvador and D Menard and E Juarez and C Sanz}, doi = {10.1109/ACCESS.2019.2934223}, issn = {2169-3536}, year = {2019}, date = {2019-01-01}, journal = {IEEE Access}, volume = {7}, pages = {111801-111812}, keywords = {}, pubstate = {published}, tppubtype = {article} } |
Palumbo, Francesca; Fanni, Tiziana; Sau, Carlo; Rodríguez, Alfonso; ñ, Daniel Madro; Desnos, Karol; Morvan, Antoine; Pelcat, Maxime; Rubattu, Claudio; Lazcano, Raquel; Raffo, Luigi; de la Torre, Eduardo; Juárez, Eduardo; Sanz, César; de Rojas, Pablo Sánchez Hardware/Software Self-adaptation in CPS: The CERBERO Project Approach Inproceedings Pnevmatikatos, Dionisios N; Pelcat, Maxime; Jung, Matthias (Ed.): Embedded Computer Systems: Architectures, Modeling, and Simulation, pp. 416–428, Springer International Publishing, Cham, 2019, ISBN: 978-3-030-27562-4. @inproceedings{Palumbo:Samos:2019, title = {Hardware/Software Self-adaptation in CPS: The CERBERO Project Approach}, author = {Francesca Palumbo and Tiziana Fanni and Carlo Sau and Alfonso Rodríguez and Daniel Madro{ñ}al and Karol Desnos and Antoine Morvan and Maxime Pelcat and Claudio Rubattu and Raquel Lazcano and Luigi Raffo and Eduardo de la Torre and Eduardo Juárez and César Sanz and Pablo Sánchez de Rojas}, editor = {Dionisios N Pnevmatikatos and Maxime Pelcat and Matthias Jung}, isbn = {978-3-030-27562-4}, year = {2019}, date = {2019-01-01}, booktitle = {Embedded Computer Systems: Architectures, Modeling, and Simulation}, pages = {416--428}, publisher = {Springer International Publishing}, address = {Cham}, abstract = {Cyber-Physical Systems (CPS) are interconnected devices, reactive and dynamic to sensed external and internal triggers. The H2020 CERBERO EU Project is developing a design environment composed by modelling, deployment and verification tools for adaptive CPS. This paper focuses on its efficient support for run-time self-adaptivity.}, keywords = {}, pubstate = {published}, tppubtype = {inproceedings} } Cyber-Physical Systems (CPS) are interconnected devices, reactive and dynamic to sensed external and internal triggers. The H2020 CERBERO EU Project is developing a design environment composed by modelling, deployment and verification tools for adaptive CPS. This paper focuses on its efficient support for run-time self-adaptivity. |
Suriano, Leonardo; Arrestier, Florian; Rodríguez, Alfonso; Heulot, Julien; Desnos, Karol; Pelcat, Maxime; de la Torre, Eduardo Microprocessors and Microsystems, 71 , pp. 102882, 2019, ISSN: 0141-9331. @article{SURIANO2019102882, title = {DAMHSE: Programming heterogeneous MPSoCs with hardware acceleration using dataflow-based design space exploration and automated rapid prototyping}, author = {Leonardo Suriano and Florian Arrestier and Alfonso Rodríguez and Julien Heulot and Karol Desnos and Maxime Pelcat and Eduardo de la Torre}, url = {http://www.sciencedirect.com/science/article/pii/S0141933118303107}, doi = {https://doi.org/10.1016/j.micpro.2019.102882}, issn = {0141-9331}, year = {2019}, date = {2019-01-01}, journal = {Microprocessors and Microsystems}, volume = {71}, pages = {102882}, abstract = {Heterogeneous Multiprocessor Systems-on-a-Chip (MPSoCs) with programmable hardware acceleration are currently gaining market share in the embedded device domain. Largest MPSoCs combine several software processing cores with programmable logic. In these systems, reaching the optimal implementation performance is difficult because many manual and time-consuming steps are required to build, from the application specification, a prototype with measurable performances. In this paper, a method is developed that, based on state-of-the-art tools and High-Level Synthesis, deploys within less than an hour a whole hardware-software rapid prototype from a unique dataflow-based application representation: DAMHSE (DAtaflow Method for Hardware/Software Exploration). A human-driven Design Space Exploration (DSE) is conducted in order to find the most performing architectural solution, and compilable/synthesizable code is generated. The method has been tested on an image processing system with software and hardware parallelism. Results show that the obtained absolute performance (pixel/cycles) reaches state-of-the-art, and that DAMHSE leads to a heterogeneous system where performance increases significantly when the application is granted with more hardware resources. One of the greatest challenges in creating such a design automation method resides in the application behavior that may change over time and affect application concurrency and system performance. In order to overcome this problem, the design-time DAtaflow Method for Hardware/Software Exploration (DAMHSE) method is complemented with a runtime application management system that dynamically dispatches jobs (tasks) among the available processing elements (CPUs and/or hardware accelerators). Experimental results show that the performance penalty due to runtime application mapping and scheduling is limited and that the computational performance of the adaptive system remains high. Apart from the vendor-specific HLS, the tools and the frameworks used by the proposed method are open source and tutorials are available to reproduce the results.}, keywords = {}, pubstate = {published}, tppubtype = {article} } Heterogeneous Multiprocessor Systems-on-a-Chip (MPSoCs) with programmable hardware acceleration are currently gaining market share in the embedded device domain. Largest MPSoCs combine several software processing cores with programmable logic. In these systems, reaching the optimal implementation performance is difficult because many manual and time-consuming steps are required to build, from the application specification, a prototype with measurable performances. In this paper, a method is developed that, based on state-of-the-art tools and High-Level Synthesis, deploys within less than an hour a whole hardware-software rapid prototype from a unique dataflow-based application representation: DAMHSE (DAtaflow Method for Hardware/Software Exploration). A human-driven Design Space Exploration (DSE) is conducted in order to find the most performing architectural solution, and compilable/synthesizable code is generated. The method has been tested on an image processing system with software and hardware parallelism. Results show that the obtained absolute performance (pixel/cycles) reaches state-of-the-art, and that DAMHSE leads to a heterogeneous system where performance increases significantly when the application is granted with more hardware resources. One of the greatest challenges in creating such a design automation method resides in the application behavior that may change over time and affect application concurrency and system performance. In order to overcome this problem, the design-time DAtaflow Method for Hardware/Software Exploration (DAMHSE) method is complemented with a runtime application management system that dynamically dispatches jobs (tasks) among the available processing elements (CPUs and/or hardware accelerators). Experimental results show that the performance penalty due to runtime application mapping and scheduling is limited and that the computational performance of the adaptive system remains high. Apart from the vendor-specific HLS, the tools and the frameworks used by the proposed method are open source and tutorials are available to reproduce the results. |
2018 |
Rubattu, C; Palumbo, F; Sau, C; Salvador, R; Serot, J; Desnos, K; Raffo, L; Pelcat, M Dataflow-Functional High-Level Synthesis for Coarse-Grained Reconfigurable Accelerators Journal Article IEEE Embedded Systems Letters, 2018, ISSN: 1943-0663. @article{Rubattu2018, title = {Dataflow-Functional High-Level Synthesis for Coarse-Grained Reconfigurable Accelerators}, author = {C. Rubattu and F. Palumbo and C. Sau and R. Salvador and J. Serot and K. Desnos and L. Raffo and M. Pelcat}, doi = {10.1109/LES.2018.2882989}, issn = {1943-0663}, year = {2018}, date = {2018-12-31}, journal = {IEEE Embedded Systems Letters}, abstract = {Domain-specific acceleration is now a "must" for all the computing spectrum, going from high performance computing to embedded systems. Unfortunately, system specialization is by nature a nightmare from the design productivity perspective. Nevertheless, in contexts where kernels to be accelerated are intrinsically streaming oriented, the combination of dataflow models of computation with Coarse-Grained Reconfigurable (CGR) architectures can be particularly handful. In this paper we introduce a novel methodology to assemble and characterize virtually reconfigurable accelerators based on dataflow and functional programming principles, capable of addressing design productivity issues for CGR accelerators. The main advantage of the proposed methodology is accurate IP-level latency predictability improving Design Space Exploration (DSE) when compared to state-of-the-art High-Level Synthesis (HLS).}, keywords = {}, pubstate = {published}, tppubtype = {article} } Domain-specific acceleration is now a "must" for all the computing spectrum, going from high performance computing to embedded systems. Unfortunately, system specialization is by nature a nightmare from the design productivity perspective. Nevertheless, in contexts where kernels to be accelerated are intrinsically streaming oriented, the combination of dataflow models of computation with Coarse-Grained Reconfigurable (CGR) architectures can be particularly handful. In this paper we introduce a novel methodology to assemble and characterize virtually reconfigurable accelerators based on dataflow and functional programming principles, capable of addressing design productivity issues for CGR accelerators. The main advantage of the proposed methodology is accurate IP-level latency predictability improving Design Space Exploration (DSE) when compared to state-of-the-art High-Level Synthesis (HLS). |
Zamacola, Rafael; Martínez, Alberto García; Mora, Javier; Otero, Andrés; de Torre, Eduardo La IMPRESS: Automated Tool for the Implementation of Highly Flexible Partial Reconfigurable Systems with Xilinx Vivado Conference Proceedings of RConFig 2018, 2018. @conference{Zamacola2018, title = {IMPRESS: Automated Tool for the Implementation of Highly Flexible Partial Reconfigurable Systems with Xilinx Vivado}, author = {Rafael Zamacola and Alberto García Martínez and Javier Mora and Andrés Otero and Eduardo de La Torre}, year = {2018}, date = {2018-12-20}, booktitle = {Proceedings of RConFig 2018}, abstract = {Dynamic partial reconfiguration is considered a great technique to increase flexibility in FPGA designs. However, partial reconfiguration flows supported by commercial tools, such as Xilinx Vivado, still have many limitations. Foremost among them are the lack of support for relocation, which leads to an increase in the on-system memory requirements and the synthesis time, as well as a reduced flexibility when it comes to the definition of reconfigurable regions. Several academic tools have appeared over the years to improve commercial flows. However, the technology shift from ISE to Vivado has left most of these tools unusable for newer FPGAs, including most of the Xilinx Series-7 devices. In this paper, authors present IMPRESS, a TCL script-based tool for the automated generation of relocatable partial bitstreams under Vivado, with a strong focus on the ease of use and the system flexibility. Special support is provided for the implementation of reconfigurable systems that include IP blocks generated with Vivado HLS and standardized bus interfaces. A stream-based reconfigurable architecture for image filtering, implemented in a fully automated manner on a Zynq SoPC, is provided as a use case of the tool.}, keywords = {}, pubstate = {published}, tppubtype = {conference} } Dynamic partial reconfiguration is considered a great technique to increase flexibility in FPGA designs. However, partial reconfiguration flows supported by commercial tools, such as Xilinx Vivado, still have many limitations. Foremost among them are the lack of support for relocation, which leads to an increase in the on-system memory requirements and the synthesis time, as well as a reduced flexibility when it comes to the definition of reconfigurable regions. Several academic tools have appeared over the years to improve commercial flows. However, the technology shift from ISE to Vivado has left most of these tools unusable for newer FPGAs, including most of the Xilinx Series-7 devices. In this paper, authors present IMPRESS, a TCL script-based tool for the automated generation of relocatable partial bitstreams under Vivado, with a strong focus on the ease of use and the system flexibility. Special support is provided for the implementation of reconfigurable systems that include IP blocks generated with Vivado HLS and standardized bus interfaces. A stream-based reconfigurable architecture for image filtering, implemented in a fully automated manner on a Zynq SoPC, is provided as a use case of the tool. |
Fanni, Tiziana; Rodríguez, Alfonso; Sau, Carlo; Suriano, Leonardo; Palumbo, Francesca; Raffo, Luigi; de la Torre, Eduardo Multi-Grain Reconfiguration for Advanced Adaptivity in Cyber- Physical Systems Conference International Conference on ReConFigurable Computing and FPGAs (ReConFig’18), IEEE, 2018. @conference{Fanni2018, title = {Multi-Grain Reconfiguration for Advanced Adaptivity in Cyber- Physical Systems}, author = {Tiziana Fanni and Alfonso Rodríguez and Carlo Sau and Leonardo Suriano and Francesca Palumbo and Luigi Raffo and Eduardo de la Torre}, year = {2018}, date = {2018-12-05}, booktitle = {International Conference on ReConFigurable Computing and FPGAs (ReConFig’18)}, publisher = {IEEE}, keywords = {}, pubstate = {published}, tppubtype = {conference} } |
Rodríguez, Alfonso; Fanni, Tiziana DEMO: Multi-Grain Adaptivity in Cyber-Physical Systems Conference Special Session on Energy Efficient Cyber Physical Systems held at the 30th International Conference onMicroelectronics (ICM’18), 2018. @conference{Rodríguez2018, title = {DEMO: Multi-Grain Adaptivity in Cyber-Physical Systems}, author = {Alfonso Rodríguez and Tiziana Fanni}, year = {2018}, date = {2018-12-05}, booktitle = {Special Session on Energy Efficient Cyber Physical Systems held at the 30th International Conference onMicroelectronics (ICM’18)}, keywords = {}, pubstate = {published}, tppubtype = {conference} } |
L., Kaliciak; H., Myrhaug; A., Goker Searching of Self-similar Spaces Conference Proceedings of the FTC 2018 - Future Technologies Conference 2018, Advances in Intelligent Systems and Computing, 2018. @conference{L.2018, title = {Searching of Self-similar Spaces}, author = {Kaliciak L. and Myrhaug H. and Goker A.}, editor = {Springer}, url = {https://www.researchgate.net/profile/Leszek_Kaliciak/publication/328409049_Searching_of_Self-similar_Spaces_Volume_2/links/5cdc1920a6fdccc9ddaeb20a/Searching-of-Self-similar-Spaces-Volume-2.pdf}, year = {2018}, date = {2018-11-21}, booktitle = {Proceedings of the FTC 2018 - Future Technologies Conference 2018, Advances in Intelligent Systems and Computing}, keywords = {}, pubstate = {published}, tppubtype = {conference} } |
L., Kaliciak; H., Myrhaug; Goker, A On Search Spaces of Fractal Nature Conference 4th International Conference on Fuzzy Systems and Data Mining, (FSDM 2018), 2018. @conference{L.2018b, title = {On Search Spaces of Fractal Nature}, author = {Kaliciak L. and Myrhaug H. and Goker, A.}, editor = {IOS Press}, year = {2018}, date = {2018-11-13}, booktitle = {4th International Conference on Fuzzy Systems and Data Mining, (FSDM 2018)}, keywords = {}, pubstate = {published}, tppubtype = {conference} } |
Suriano, Leonardo; Madroñal, Daniel; Rodríguez, Alfonso; Juárez, Eduardo; Sanz, César; de la Torre, Eduardo A Unified Hardware/Software Monitoring Method for Reconfigurable Computing Architectures using PAPI Conference 2018 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), IEEE, 2018. @conference{Suriano2018, title = {A Unified Hardware/Software Monitoring Method for Reconfigurable Computing Architectures using PAPI}, author = {Leonardo Suriano and Daniel Madroñal and Alfonso Rodríguez and Eduardo Juárez and César Sanz and Eduardo de la Torre}, url = {http://oa.upm.es/51783/ }, year = {2018}, date = {2018-07-21}, booktitle = {2018 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)}, publisher = {IEEE}, keywords = {}, pubstate = {published}, tppubtype = {conference} } |
Arrestier, Florian; Desnos, Karol; Pelcat, Maxime; Heulot, Julien; Juarez, Eduardo; Menard, Daniel Delays and States in Dataflow Models of Computation Conference Proceedings of the SAMOS 2018 Conference, 2018. @conference{Arrestier2018, title = {Delays and States in Dataflow Models of Computation}, author = {Florian Arrestier and Karol Desnos and Maxime Pelcat and Julien Heulot and Eduardo Juarez and Daniel Menard}, year = {2018}, date = {2018-07-19}, booktitle = {Proceedings of the SAMOS 2018 Conference}, abstract = {Dataflow Models of Computation (MoCs) have proven efficient means for modeling computational aspects of Cyber-Physical Systems.Over the years, diverse MoCs have been proposed that offer trade-offs between expressivity, conciseness, predictability, and reconfigurability. While being efficient for modeling coarse grain data and task parallelism, state-of-the-art dataflow MoCs suffer from a lack of semantics to benefit from the lower grained parallelism offered by hierarchically modeled nested loops. In this paper, a meta-model called State-Aware Dataflow (SAD) is proposed that enhances a dataflow MoC, introducing new semantics to take advantage of such nested loop parallelism. SAD extends the semantics of the targeted MoC with unambiguous data persistence scope. The extended expressiveness and conciseness brought by the SAD meta-model are demonstrated with a reinforcement learning use-case.}, keywords = {}, pubstate = {published}, tppubtype = {conference} } Dataflow Models of Computation (MoCs) have proven efficient means for modeling computational aspects of Cyber-Physical Systems.Over the years, diverse MoCs have been proposed that offer trade-offs between expressivity, conciseness, predictability, and reconfigurability. While being efficient for modeling coarse grain data and task parallelism, state-of-the-art dataflow MoCs suffer from a lack of semantics to benefit from the lower grained parallelism offered by hierarchically modeled nested loops. In this paper, a meta-model called State-Aware Dataflow (SAD) is proposed that enhances a dataflow MoC, introducing new semantics to take advantage of such nested loop parallelism. SAD extends the semantics of the targeted MoC with unambiguous data persistence scope. The extended expressiveness and conciseness brought by the SAD meta-model are demonstrated with a reinforcement learning use-case. |
Madroñal, Daniel; Morvan, Antoine; Lazcano, Raquel; Salvador, Rubén; Desnos, Karol; Juárez, Eduardo; Sanz, César Automatic Instrumentation of Dataflow Applications using PAPI Conference 15th ACM International Conference on Computing Frontiers (CF'18), ACM, 2018. @conference{Madroñal2018, title = {Automatic Instrumentation of Dataflow Applications using PAPI}, author = {Daniel Madroñal and Antoine Morvan and Raquel Lazcano and Rubén Salvador and Karol Desnos and Eduardo Juárez and César Sanz}, url = {https://www.researchgate.net/publication/325217267_Automatic_Instrumentation_of_Dataflow_Applications_using_PAPI https://www.cerbero-h2020.eu/wp-content/uploads/2018/06/Poster-CF18.pdf}, doi = {10.1145/3203217.3209886}, year = {2018}, date = {2018-05-08}, booktitle = {15th ACM International Conference on Computing Frontiers (CF'18)}, pages = {232-235}, publisher = {ACM}, abstract = {The widening of the complexity-productivity gap witnessed in the last years is becoming unaffordable from the application development point of view. New design methods try to automate most designers tasks in order to bridge this gap. In addition, new Models of Computation (MoC), as those dataflow-based, ease the expression of parallelism within applications and lead to higher productivity. Rapid prototyping design tools offer fast estimations of the soundness of design choices. A key step when prototyping an application is to have representative performance indicators to estimate the validity of the design choices. Such indicators can be obtained using hardware information through the Performance API (PAPI). In this work, PAPI and a dataflow MoC are integrated within a Y-chart design flow. The implementation takes the form of a dedicated automatic code generation scheme within the Preesm tool. Preliminary results show that depending on the complexity of the application, the computation time overhead due to monitoring varies from being almost negligible to more than 50%. Also, on top of offering accurate hardware performance indicators, the extracted values can be combined to estimate power or energy consumption. }, keywords = {}, pubstate = {published}, tppubtype = {conference} } The widening of the complexity-productivity gap witnessed in the last years is becoming unaffordable from the application development point of view. New design methods try to automate most designers tasks in order to bridge this gap. In addition, new Models of Computation (MoC), as those dataflow-based, ease the expression of parallelism within applications and lead to higher productivity. Rapid prototyping design tools offer fast estimations of the soundness of design choices. A key step when prototyping an application is to have representative performance indicators to estimate the validity of the design choices. Such indicators can be obtained using hardware information through the Performance API (PAPI). In this work, PAPI and a dataflow MoC are integrated within a Y-chart design flow. The implementation takes the form of a dedicated automatic code generation scheme within the Preesm tool. Preliminary results show that depending on the complexity of the application, the computation time overhead due to monitoring varies from being almost negligible to more than 50%. Also, on top of offering accurate hardware performance indicators, the extracted values can be combined to estimate power or energy consumption. |
Narizzano, Massimo; Pulina, Luca; Tacchella, Armando; Simone, Vuotto Consistency of property specification patterns with boolean and constrained numerical signals Conference NASA Formal Methods Symposium, 2018, ISBN: 978-3-319-77935-5. @conference{Narizzano2018, title = {Consistency of property specification patterns with boolean and constrained numerical signals}, author = {Massimo Narizzano and Luca Pulina and Armando Tacchella and Vuotto Simone}, isbn = {978-3-319-77935-5}, year = {2018}, date = {2018-04-17}, booktitle = {NASA Formal Methods Symposium}, pages = {383--398}, abstract = {Property Specification Patterns (PSPs) have been proposed to solve recurring specification needs, to ease the formalization of requirements, and enable automated verification thereof. In this paper, we extend PSPs by considering Boolean as well as atomic numerical assertions. This extension enables us to reason about functional requirements which would not be captured by basic PSPs. We contribute an encoding from constrained PSPs to LTL formulae, and we show experimental results demonstrating that our approach scales on requirements of realistic size generated using a probabilistic model. Finally, we show that our extension enables us to prove (in)consistency of requirements about an embedded controller for a robotic manipulator.}, keywords = {}, pubstate = {published}, tppubtype = {conference} } Property Specification Patterns (PSPs) have been proposed to solve recurring specification needs, to ease the formalization of requirements, and enable automated verification thereof. In this paper, we extend PSPs by considering Boolean as well as atomic numerical assertions. This extension enables us to reason about functional requirements which would not be captured by basic PSPs. We contribute an encoding from constrained PSPs to LTL formulae, and we show experimental results demonstrating that our approach scales on requirements of realistic size generated using a probabilistic model. Finally, we show that our extension enables us to prove (in)consistency of requirements about an embedded controller for a robotic manipulator. |
Rubattu, Claudio Dataflow-based Adaptation Framework with Coarse-Grained Reconfigurable Accelerators Conference CEUR Workshop Proceedings - Proceedings of the Cyber-Physical Systems PhD & Postdoc Workshop 2018, 2018. @conference{Rubattu2018b, title = {Dataflow-based Adaptation Framework with Coarse-Grained Reconfigurable Accelerators}, author = {Claudio Rubattu}, url = {http://ceur-ws.org/Vol-2208/5.pdf}, year = {2018}, date = {2018-04-05}, booktitle = {CEUR Workshop Proceedings - Proceedings of the Cyber-Physical Systems PhD & Postdoc Workshop 2018}, abstract = {Today, the demand of adaptive systems is constantly growing, especially in hard-constrained contexts such as Cyber-Physical Systems. However, the efficient management of such platforms requires dealing with several issues such as the real-time execution, energy saving and dynamic context changes. Such strict requirements imply a high flexibility of the application and of the architecture on which it is executed. Runtime managers offer the possibility to dynamically schedule and map an application on the available software processing units. However, hardware acceleration may also be necessary for computationally-intensive workloads that depend on the running functionality, additionally complicating runtime management. Coarse-Grained Reconfigurable (CGR) accelerators have the ability to switch among different domain-specific functionalities with a small overhead. To support energy and time adaptivity in heterogeneous systems, and to exploit multi-core architectures and CGR accelerators, this work proposes the combination of the SPIDER software runtime manager and the dataflow-to-hardware MDC design suite for CGR accelerators.}, keywords = {}, pubstate = {published}, tppubtype = {conference} } Today, the demand of adaptive systems is constantly growing, especially in hard-constrained contexts such as Cyber-Physical Systems. However, the efficient management of such platforms requires dealing with several issues such as the real-time execution, energy saving and dynamic context changes. Such strict requirements imply a high flexibility of the application and of the architecture on which it is executed. Runtime managers offer the possibility to dynamically schedule and map an application on the available software processing units. However, hardware acceleration may also be necessary for computationally-intensive workloads that depend on the running functionality, additionally complicating runtime management. Coarse-Grained Reconfigurable (CGR) accelerators have the ability to switch among different domain-specific functionalities with a small overhead. To support energy and time adaptivity in heterogeneous systems, and to exploit multi-core architectures and CGR accelerators, this work proposes the combination of the SPIDER software runtime manager and the dataflow-to-hardware MDC design suite for CGR accelerators. |
Vuotto, Simone Consistency Checking of Functional Requirements Conference Proceedings of the Doctoral Consortium of Formal Methods 2018, 2018. @conference{Vuotto2018b, title = {Consistency Checking of Functional Requirements}, author = {Simone Vuotto}, url = {https://arxiv.org/pdf/1804.10486.pdf}, year = {2018}, date = {2018-03-15}, booktitle = {Proceedings of the Doctoral Consortium of Formal Methods 2018}, keywords = {}, pubstate = {published}, tppubtype = {conference} } |
Bit-Monnot, Arthur Goal Based Deliberation of Cyber-Physical Systems Conference Cyber-Physical systems PhD and Post-doc workshop, 2018. @conference{Bit-Monnot2018b, title = {Goal Based Deliberation of Cyber-Physical Systems}, author = {Arthur Bit-Monnot}, url = {http://ceur-ws.org/Vol-2208/1.pdf}, year = {2018}, date = {2018-03-08}, booktitle = {Cyber-Physical systems PhD and Post-doc workshop}, keywords = {}, pubstate = {published}, tppubtype = {conference} } |
Vuotto, Simone Requirements-driven design of cyber-physical systems Conference Cyber-Physical systems PhD and Post-doc workshop, 2018. @conference{Vuotto2018, title = {Requirements-driven design of cyber-physical systems}, author = {Simone Vuotto}, url = { http://ceur-ws.org/Vol-2208/6.pdf}, year = {2018}, date = {2018-03-08}, booktitle = {Cyber-Physical systems PhD and Post-doc workshop}, keywords = {}, pubstate = {published}, tppubtype = {conference} } |
Pilato, Christian; Carloni, Luca P DarkMem: Fine-grained power management of local memories for accelerators in embedded systems Conference 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), IEEE, 2018, ISBN: 978-1-5090-0602-1. @conference{Pilato2018, title = {DarkMem: Fine-grained power management of local memories for accelerators in embedded systems}, author = {Christian Pilato and Luca P. Carloni}, url = {http://people.alari.ch/pilato/pdf/aspdac18-darkmem.pdf}, doi = {10.1109/ASPDAC.2018.8297403}, isbn = {978-1-5090-0602-1}, year = {2018}, date = {2018-01-22}, booktitle = {2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC)}, publisher = {IEEE}, abstract = {SRAM consumes a growing fraction of the static power in heterogeneous SoCs, as embedded memories take 70% to 90% of the area of specialized accelerators. We present Dark-Mem as a comprehensive solution for fine-grained power management of accelerator local memories. The DarkMem methodology optimizes at design time the bank configuration for each given accelerator to maximize power-gating opportunities. The DarkMem microarchitecture dynamically varies the operating mode of each memory bank according to the accelerator workload. In our experiments, DarkMem reduces the SRAM static power by more than 40% on average, which translates into a reduction of the total power by almost 18% on average with less than 1% overhead.}, keywords = {}, pubstate = {published}, tppubtype = {conference} } SRAM consumes a growing fraction of the static power in heterogeneous SoCs, as embedded memories take 70% to 90% of the area of specialized accelerators. We present Dark-Mem as a comprehensive solution for fine-grained power management of accelerator local memories. The DarkMem methodology optimizes at design time the bank configuration for each given accelerator to maximize power-gating opportunities. The DarkMem microarchitecture dynamically varies the operating mode of each memory bank according to the accelerator workload. In our experiments, DarkMem reduces the SRAM static power by more than 40% on average, which translates into a reduction of the total power by almost 18% on average with less than 1% overhead. |
2017 |
Rubattu, Claudio; Palumbo, Francesca; Pelcat, Maxime Adaptive Software-Augmented Hardware Reconfiguration with Dataflow Design Automation Conference 2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2017, ISBN: 978-1-5386-3797-5. @conference{Rubattu2017, title = {Adaptive Software-Augmented Hardware Reconfiguration with Dataflow Design Automation}, author = {Claudio Rubattu and Francesca Palumbo and Maxime Pelcat}, url = {https://www.researchgate.net/publication/322943749_Adaptive_software-augmented_hardware_reconfiguration_with_dataflow_design_automation https://www.cerbero-h2020.eu/wp-content/uploads/2018/09/ReConFig2017_Rubattu_et_al.pdf }, doi = {10.1109/RECONFIG.2017.8279772 }, isbn = {978-1-5386-3797-5}, year = {2017}, date = {2017-12-04}, booktitle = {2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher = {IEEE}, abstract = {Demand of adaptive hard-constrained devices is continuing to increase. Developing efficient implementations of such systems means to address trade-offs among different specifications, i.e. real-time processing, low power consumption and partial context switching at runtime. In this PhD Plan, we will focus on the hardware perspective presenting how we intend to study and experience with adaptive co-processing architectures, considering software as a supporting element.}, keywords = {}, pubstate = {published}, tppubtype = {conference} } Demand of adaptive hard-constrained devices is continuing to increase. Developing efficient implementations of such systems means to address trade-offs among different specifications, i.e. real-time processing, low power consumption and partial context switching at runtime. In this PhD Plan, we will focus on the hardware perspective presenting how we intend to study and experience with adaptive co-processing architectures, considering software as a supporting element. |
Pelcat, Maxime; Mercat, Alexandre; Desnos, Karol; Maggiani, Luca; Liu, Yanzhou; Heulot, Julien; Nezan, Jean-François; Hamidouche, Wassim; Ménard, Daniel; Bhattacharyya, Shuvra S Reproducible Evaluation of System Efficiency with a Model of Architecture: From Theory to Practice Journal Article IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2017, ISSN: 1937-4151. @article{Pelcat2017, title = {Reproducible Evaluation of System Efficiency with a Model of Architecture: From Theory to Practice}, author = {Maxime Pelcat and Alexandre Mercat and Karol Desnos and Luca Maggiani and Yanzhou Liu and Julien Heulot and Jean-François Nezan and Wassim Hamidouche and Daniel Ménard and Shuvra S. Bhattacharyya}, url = {https://hal.archives-ouvertes.fr/hal-01646738/file/tcad_mpelcat17.pdf https://ieeexplore.ieee.org/document/8114259/}, doi = {10.1109/TCAD.2017.2774822}, issn = {1937-4151}, year = {2017}, date = {2017-11-17}, journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}, abstract = {Current trends in high performance and embedded computing include design of increasingly complex hardware architectures with high parallelism, heterogeneous processing elements and non-uniform communication resources. In order to take hardware and software design decisions, early evaluations of the system non-functional properties are needed. These evaluations of system efficiency require Electronic System-Level (ESL) information on both the algorithms and the architecture. Contrary to algorithm models for which a major body of work has been conducted on defining formal Models of Computation (MoCs), architecture models from the literature are mostly empirical models from which reproducible experimentation requires the accompanying software. In this paper, a precise definition of a Model of Architecture (MoA) is proposed that focuses on reproducibility and abstraction and removes the overlap previously existing between the notions of MoA and MoC. A first MoA, called the Linear System-Level Architecture Model (LSLA), is presented. To demonstrate the generic nature of the proposed new architecture modeling concepts, we show that the LSLA Model can be integrated flexibly with different MoCs. LSLA is then used to model the energy consumption of a State-of-the-Art Multiprocessor System-on-Chip (MPSoC) when running an application described using the Synchronous Dataflow (SDF) MoC. A method to automatically learn LSLA model parameters from platform measurements is introduced. Despite the high complexity of the underlying hardware and software, a simple LSLA model is demonstrated to estimate the energy consumption of the MPSoC with a fidelity of 86%.}, keywords = {}, pubstate = {published}, tppubtype = {article} } Current trends in high performance and embedded computing include design of increasingly complex hardware architectures with high parallelism, heterogeneous processing elements and non-uniform communication resources. In order to take hardware and software design decisions, early evaluations of the system non-functional properties are needed. These evaluations of system efficiency require Electronic System-Level (ESL) information on both the algorithms and the architecture. Contrary to algorithm models for which a major body of work has been conducted on defining formal Models of Computation (MoCs), architecture models from the literature are mostly empirical models from which reproducible experimentation requires the accompanying software. In this paper, a precise definition of a Model of Architecture (MoA) is proposed that focuses on reproducibility and abstraction and removes the overlap previously existing between the notions of MoA and MoC. A first MoA, called the Linear System-Level Architecture Model (LSLA), is presented. To demonstrate the generic nature of the proposed new architecture modeling concepts, we show that the LSLA Model can be integrated flexibly with different MoCs. LSLA is then used to model the energy consumption of a State-of-the-Art Multiprocessor System-on-Chip (MPSoC) when running an application described using the Synchronous Dataflow (SDF) MoC. A method to automatically learn LSLA model parameters from platform measurements is introduced. Despite the high complexity of the underlying hardware and software, a simple LSLA model is demonstrated to estimate the energy consumption of the MPSoC with a fidelity of 86%. |
Pilato, Christian; Garg, Siddharth; Wu, Kaijie; Karri, Ramesh; Regazzoni, Francesco Securing Hardware Accelerators: a New Challenge for High-Level Synthesis (Perspective Paper) Journal Article IEEE Embedded Systems Letters, 2017, ISBN: 1943-0671. @article{Pilato2017, title = {Securing Hardware Accelerators: a New Challenge for High-Level Synthesis (Perspective Paper)}, author = {Christian Pilato and Siddharth Garg and Kaijie Wu and Ramesh Karri and Francesco Regazzoni}, url = {http://people.alari.ch/pilato/pdf/esl17-securityhls.pdf}, doi = {10.1109/LES.2017.2774800}, isbn = {1943-0671}, year = {2017}, date = {2017-11-17}, journal = {IEEE Embedded Systems Letters}, abstract = {High-level synthesis (HLS) tools have made significant progress in the past few years, improving the design productivity for hardware accelerators and becoming mainstream in industry to create specialized System-on-Chip (SoC) architectures. Increasing the level of security of these heterogeneous architectures is becoming critical. However, state-of-the-art security countermeasures are still applied only to the code executing on the processor cores or manually implemented into the generated components, leading to suboptimal and sometimes even insecure designs. This paper discusses extensions to HLS tools for creating secure heterogeneous architectures.}, keywords = {}, pubstate = {published}, tppubtype = {article} } High-level synthesis (HLS) tools have made significant progress in the past few years, improving the design productivity for hardware accelerators and becoming mainstream in industry to create specialized System-on-Chip (SoC) architectures. Increasing the level of security of these heterogeneous architectures is becoming critical. However, state-of-the-art security countermeasures are still applied only to the code executing on the processor cores or manually implemented into the generated components, leading to suboptimal and sometimes even insecure designs. This paper discusses extensions to HLS tools for creating secure heterogeneous architectures. |
Palumbo, Francesca; Sau, Carlo; Fanni, Tiziana; Raffo, Luigi Challenging CPS Trade-Off Adaptivity with Coarse-Grained Reconfiguration Conference Applications in Electronics Pervading Industry, Environment and Society (ApplePies 2017), Lecture Notes in Electrical Engineering, 512 , Springer, 2017, ISBN: 978-3-319-93082-4. @conference{Palumbo2017b, title = {Challenging CPS Trade-Off Adaptivity with Coarse-Grained Reconfiguration}, author = {Francesca Palumbo and Carlo Sau and Tiziana Fanni and Luigi Raffo}, url = {https://www.cerbero-h2020.eu/wp-content/uploads/2018/07/RG_ApplePies2017.pdf https://www.cerbero-h2020.eu/wp-content/uploads/2017/10/tfanni_APPLEPIES_2017.pdf https://www.researchgate.net/publication/320282531_Challenging_CPS_Trade-Off_Adaptivity_with_Coarse-Grained_Reconfiguration}, doi = {10.1007/978-3-319-93082-4_8}, isbn = {978-3-319-93082-4}, year = {2017}, date = {2017-09-21}, booktitle = {Applications in Electronics Pervading Industry, Environment and Society (ApplePies 2017), Lecture Notes in Electrical Engineering}, journal = {Applications in Electronics Pervading Industry, Environment and Society Conference (ApplePies)}, volume = {512}, pages = {57-63}, publisher = {Springer}, abstract = {Cyber Physical Systems are highly adaptive systems, prone to change behaviour due to external/internal conditions. From the computation point of view, reconfigurable systems may address adaptation. In this paper, by a set of examples we show how coarse-grained reconfiguration may successfully allow achieving dynamic trade-off management, while considering different technology targets and different design flows. }, keywords = {}, pubstate = {published}, tppubtype = {conference} } Cyber Physical Systems are highly adaptive systems, prone to change behaviour due to external/internal conditions. From the computation point of view, reconfigurable systems may address adaptation. In this paper, by a set of examples we show how coarse-grained reconfiguration may successfully allow achieving dynamic trade-off management, while considering different technology targets and different design flows. |
Suriano, Leonardo; Rodríguez, Alfonso; Desnos, Karol; Pelcat, Maxime; de la Torre, Eduardo 2017 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), IEEE, 2017, ISBN: 978-1-5386-3344-1. @conference{Suriano2017, title = {Analysis of a Heterogeneous Multi-Core, Multi-HW-Accelerator-Based System Designed Using PREESM and SDSoC}, author = {Leonardo Suriano and Alfonso Rodríguez and Karol Desnos and Maxime Pelcat and Eduardo de la Torre}, url = {http://oa.upm.es/51778/ https://www.cerbero-h2020.eu/wp-content/uploads/2017/10/Presentation-ReCoSoC_2017.pdf }, doi = {10.1109/ReCoSoC.2017.8016151}, isbn = {978-1-5386-3344-1}, year = {2017}, date = {2017-07-12}, booktitle = {2017 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)}, journal = {12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)}, publisher = {IEEE}, abstract = {Nowadays, new heterogeneous system technologies are flooding the market: through the past years, it is possible to observe the move from single CPUs to multi-core devices featuring CPUs, GPUs and large FPGAs, such as Xilinx Zynq-7000 or Zynq UltraScale+ MPSoC architectures. In this context, providing developers with transparent deployment capabilities to efficiently execute different applications on such complex devices is important. In this paper, a design flow that combines, on one side, PREESM, a dataflow-based prototyping framework and, on the other side, Xilinx SDSoC, an HLS-based framework to automatically generate and manage hardware accelerators, is presented. This integration leverages the automatic, static task scheduling obtained from PREESM with asynchronous invocations that trigger the parallel execution of multiple hardware accelerators from some of their associated sequential software threads. An image processing application is used as a proof of concept, showing the interoperability possibilities of both tools, the level of design automation achieved and, for the resulting computing architecture, the good performance scalability according to the number of accelerators and sw threads.}, keywords = {}, pubstate = {published}, tppubtype = {conference} } Nowadays, new heterogeneous system technologies are flooding the market: through the past years, it is possible to observe the move from single CPUs to multi-core devices featuring CPUs, GPUs and large FPGAs, such as Xilinx Zynq-7000 or Zynq UltraScale+ MPSoC architectures. In this context, providing developers with transparent deployment capabilities to efficiently execute different applications on such complex devices is important. In this paper, a design flow that combines, on one side, PREESM, a dataflow-based prototyping framework and, on the other side, Xilinx SDSoC, an HLS-based framework to automatically generate and manage hardware accelerators, is presented. This integration leverages the automatic, static task scheduling obtained from PREESM with asynchronous invocations that trigger the parallel execution of multiple hardware accelerators from some of their associated sequential software threads. An image processing application is used as a proof of concept, showing the interoperability possibilities of both tools, the level of design automation achieved and, for the resulting computing architecture, the good performance scalability according to the number of accelerators and sw threads. |
Kaliciak, Leszek; Myrhaug, Hans; Goker, Ayse Unified Hybrid Image Retrieval System with Continuous Relevance Feedback Conference 1 , IIIS, 2017, ISBN: 978-1-941763-59-9. @conference{Kaliciak2017, title = {Unified Hybrid Image Retrieval System with Continuous Relevance Feedback}, author = {Leszek Kaliciak and Hans Myrhaug and Ayse Goker}, url = {https://www.cerbero-h2020.eu/wp-content/uploads/2017/10/Presentation-WMSCI_2017.pdf https://www.researchgate.net/publication/320623929_Unified_Hybrid_Image_Retrieval_System_with_Continuous_Relevance_Feedback}, isbn = {978-1-941763-59-9}, year = {2017}, date = {2017-07-08}, journal = {The 21st World Multi-Conference on Systemics, Cybernetics and Informatics (WMSCI)}, volume = {1}, pages = {275-280}, publisher = {IIIS}, abstract = {In this paper, we present a unified hybrid image retrieval system consisting of the following components: various visual features and their combinations, combination of visual and textual feature spaces, combination of visual and textual feature spaces in the context of search refinement, and interactive user interface with hybrid relevance feedback, exploratory search, query history, relevance bar, and positive and negative results panels. In the paper we also introduce two novel hybrid spinoff models and describe the new continuous relevance feedback framework that allows us to move away from graded relevance and shows the relationships between feedback images.}, keywords = {}, pubstate = {published}, tppubtype = {conference} } In this paper, we present a unified hybrid image retrieval system consisting of the following components: various visual features and their combinations, combination of visual and textual feature spaces, combination of visual and textual feature spaces in the context of search refinement, and interactive user interface with hybrid relevance feedback, exploratory search, query history, relevance bar, and positive and negative results panels. In the paper we also introduce two novel hybrid spinoff models and describe the new continuous relevance feedback framework that allows us to move away from graded relevance and shows the relationships between feedback images. |
Kaliciak, Leszek; Myrhaug, Hans; Goker, Ayse Content-Based Image Retrieval in Augmented Reality Conference 615 , Advances in Intelligent Systems and Computing series Springer International Publishing AG, 2017, ISBN: 9783319611174. @conference{Kaliciak2017b, title = {Content-Based Image Retrieval in Augmented Reality}, author = {Leszek Kaliciak and Hans Myrhaug and Ayse Goker}, url = {https://www.cerbero-h2020.eu/wp-content/uploads/2017/10/Presentation-ISAMI_2017.pdf https://www.researchgate.net/publication/318179015_Content-Based_Image_Retrieval_in_Augmented_Reality}, doi = {https://doi.org/10.1007/978-3-319-61118-1_13}, isbn = {9783319611174}, year = {2017}, date = {2017-06-15}, volume = {615}, publisher = {Springer International Publishing AG}, series = {Advances in Intelligent Systems and Computing series}, abstract = {In this paper, we present a content-based image retrieval framework which augments the user’s reality and supports the decision making process as well as awareness and understanding of the local marine environment. It comprises a real-time intelligent user interface combined with the 360 ∘∘ real-time environment display in the virtual reality headset. The image retrieval utilizes a unified hybrid adaptive image retrieval model. The presented system provides the user with a unique solution combining the virtual reality real-time headset, 360 ∘∘ view, and augmented reality to remotely monitor the surface and underwater marine environment. The objective of the proposed framework is to enhance the user interaction with the remote sensing and control applications. To our knowledge, it is the first system that combines real-time VR, 360 ∘∘ camera, and hybrid models in the context of image retrieval and augmented reality.}, keywords = {}, pubstate = {published}, tppubtype = {conference} } In this paper, we present a content-based image retrieval framework which augments the user’s reality and supports the decision making process as well as awareness and understanding of the local marine environment. It comprises a real-time intelligent user interface combined with the 360 ∘∘ real-time environment display in the virtual reality headset. The image retrieval utilizes a unified hybrid adaptive image retrieval model. The presented system provides the user with a unique solution combining the virtual reality real-time headset, 360 ∘∘ view, and augmented reality to remotely monitor the surface and underwater marine environment. The objective of the proposed framework is to enhance the user interaction with the remote sensing and control applications. To our knowledge, it is the first system that combines real-time VR, 360 ∘∘ camera, and hybrid models in the context of image retrieval and augmented reality. |
Sau, Carlo; Palumbo, Francesca; Pelcat, Maxime; Heulot, Julien; Nogues, Erwan; Menard, Daniel; Meloni, Paolo; Raffo, Luigi Challenging the Best HEVC Fractional Pixel FPGA Interpolators with Reconfigurable and Multi-frequency Approximate Computing Journal Article IEEE Embedded Systems Letters, 9 (3), pp. 65-68, 2017, ISSN: 1943-0663. @article{Sau2017, title = {Challenging the Best HEVC Fractional Pixel FPGA Interpolators with Reconfigurable and Multi-frequency Approximate Computing}, author = {Carlo Sau and Francesca Palumbo and Maxime Pelcat and Julien Heulot and Erwan Nogues and Daniel Menard and Paolo Meloni and Luigi Raffo}, doi = {10.1109/LES.2017.2703585}, issn = {1943-0663}, year = {2017}, date = {2017-05-23}, journal = {IEEE Embedded Systems Letters}, volume = {9}, number = {3}, pages = {65-68}, publisher = {IEEE}, abstract = {Applicable in different fields and markets, low energy high efficiency video coding (HEVC) codecs and their constituting elements have been heavily studied. Fractional pixel interpolation is one of its most costly blocks. In this letter, a field programmable gate array implementation of HEVC fractional pixel interpolation, outperforming literature solutions, is proposed. Approximate computing, in conjunction with hardware reconfiguration, guarantees a tunable interpolation system offering an energy versus quality tradeoff to further reduce energy.}, keywords = {}, pubstate = {published}, tppubtype = {article} } Applicable in different fields and markets, low energy high efficiency video coding (HEVC) codecs and their constituting elements have been heavily studied. Fractional pixel interpolation is one of its most costly blocks. In this letter, a field programmable gate array implementation of HEVC fractional pixel interpolation, outperforming literature solutions, is proposed. Approximate computing, in conjunction with hardware reconfiguration, guarantees a tunable interpolation system offering an energy versus quality tradeoff to further reduce energy. |
Masin, M; Palumbo, F; Myrhaug, H; de Filho, Oliveira J A; Pastena, M; Pelcat, M; Raffo, L; Regazzoni, F; Sanchez, A A; Toffetti, A; de la Torre, E; Zedda, K Cross-layer Design of Reconfigurable Cyber-Physical Systems Conference Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, IEEE, 2017, ISSN: 1558-1101. @conference{Masin2017, title = {Cross-layer Design of Reconfigurable Cyber-Physical Systems}, author = {M.. Masin and F. Palumbo and H. Myrhaug and J. A. de Oliveira Filho and M. Pastena and M. Pelcat and L. Raffo and F. Regazzoni and A. A. Sanchez and A. Toffetti and E. de la Torre and K. Zedda}, url = {https://www.cerbero-h2020.eu/wp-content/uploads/2017/10/date17-CERBERO-v1.0.pdf}, doi = {10.23919/DATE.2017.7927088}, issn = {1558-1101}, year = {2017}, date = {2017-05-15}, booktitle = {Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017}, journal = {2017 Design, Automation & Test in Europe Conference & Exhibition (DATE)}, publisher = {IEEE}, abstract = {In the last few years, besides the concepts of embedded and interconnected systems, also the notion of Cyber-Physical Systems (CPS) has emerged: embedded computational collaborating devices, capable of sensing and controlling physical elements and, often, responding to humans. The continuous interaction between physical and computing layers makes their design and maintenance extremely complex. Uncertainty management and runtime reconfigurability, to mention the most relevant ones, are rarely tackled by available toolchains. In this context, the Cross-layer modEl-based fRamework for multi-oBjective dEsign of Reconfigurable systems in unceRtain hybRid envirOnments (CERBERO) EU project aims at developing a design environment for CPS based of two pillars: 1) a cross-layer model-based approach to describe, optimize, and analyze the system and all its different views concurrently and 2) an advanced adaptivity support based on a multi-layer autonomous engine. In this work, we describe the components and the required developments for seamless design of reusable and reconfigurable CPS and System of Systems in uncertain hybrid environments.}, keywords = {}, pubstate = {published}, tppubtype = {conference} } In the last few years, besides the concepts of embedded and interconnected systems, also the notion of Cyber-Physical Systems (CPS) has emerged: embedded computational collaborating devices, capable of sensing and controlling physical elements and, often, responding to humans. The continuous interaction between physical and computing layers makes their design and maintenance extremely complex. Uncertainty management and runtime reconfigurability, to mention the most relevant ones, are rarely tackled by available toolchains. In this context, the Cross-layer modEl-based fRamework for multi-oBjective dEsign of Reconfigurable systems in unceRtain hybRid envirOnments (CERBERO) EU project aims at developing a design environment for CPS based of two pillars: 1) a cross-layer model-based approach to describe, optimize, and analyze the system and all its different views concurrently and 2) an advanced adaptivity support based on a multi-layer autonomous engine. In this work, we describe the components and the required developments for seamless design of reusable and reconfigurable CPS and System of Systems in uncertain hybrid environments. |
Pulina, Luca; Tacchella, Armando More adaptive does not imply less safe (with formal verification) Conference Hardware and Software: Verification and Testing -13th International Haifa Verification Conference, Springer, Cham, 2017. @conference{Pulina2017, title = {More adaptive does not imply less safe (with formal verification)}, author = {Luca Pulina and Armando Tacchella}, url = {https://www.cerbero-h2020.eu/wp-content/uploads/2020/02/HVC.pdf}, year = {2017}, date = {2017-03-01}, booktitle = {Hardware and Software: Verification and Testing -13th International Haifa Verification Conference}, publisher = {Springer, Cham}, keywords = {}, pubstate = {published}, tppubtype = {conference} } |
Other Non-Indexed Technical Presentations
2018 |
Palumbo, Francesca; Rubattu, Claudio; Sau, Carlo; Raffo, Luigi; Pelcat, Maxime Platform-Agnostic Dataflow-to-Hardware Design Flow for Reconfigurable Systems Miscellaneous 2018. @misc{Palumbo2018, title = {Platform-Agnostic Dataflow-to-Hardware Design Flow for Reconfigurable Systems}, author = {Francesca Palumbo and Claudio Rubattu and Carlo Sau and Luigi Raffo and Maxime Pelcat}, url = {https://www.cerbero-h2020.eu/wp-content/uploads/2018/06/Sau_SIE2018.pdf}, year = {2018}, date = {2018-06-20}, keywords = {}, pubstate = {published}, tppubtype = {misc} } |
Sau, Carlo; Fanni, Tiziana; Raffo, Luigi; Palumbo, Francesca Self-adaptation of Cyber-Physical Systems Miscellaneous 2018. @misc{Sau2018, title = {Self-adaptation of Cyber-Physical Systems}, author = {Carlo Sau and Tiziana Fanni and Luigi Raffo and Francesca Palumbo}, url = {https://www.cerbero-h2020.eu/wp-content/uploads/2018/06/Sau_SIE2018_2.pdf}, year = {2018}, date = {2018-06-20}, keywords = {}, pubstate = {published}, tppubtype = {misc} } |
2017 |
Palumbo, Francesca; Rubattu, Claudio; Sau, Carlo; Fanni, Tiziana; Meloni, Paolo; Raffo, Luigi Dynamic Trade-Off Management for CPS Miscellaneous 2017. @misc{Palumbo2017, title = {Dynamic Trade-Off Management for CPS}, author = {Francesca Palumbo and Claudio Rubattu and Carlo Sau and Tiziana Fanni and Paolo Meloni and Luigi Raffo}, url = {http://mclab.di.uniroma1.it/iwes2017/presentations.phtml?id=palumbo1}, year = {2017}, date = {2017-09-08}, journal = {IWES2017}, abstract = {Functional approximate computing methodologies combined with coarse-grained reconfigurable design approaches are prospectively suitable to address variable run-time trade-off management typical of evolvable and adaptive cyber-physical systems. This abstract presents preliminary achievements in HEVC interpolation filters acceleration to be used to trade quality for energy in an ocean monitoring use case to be developed in an H2020 project.}, keywords = {}, pubstate = {published}, tppubtype = {misc} } Functional approximate computing methodologies combined with coarse-grained reconfigurable design approaches are prospectively suitable to address variable run-time trade-off management typical of evolvable and adaptive cyber-physical systems. This abstract presents preliminary achievements in HEVC interpolation filters acceleration to be used to trade quality for energy in an ocean monitoring use case to be developed in an H2020 project. |
Palumbo, Francesca; Sau, Carlo; Meloni, Paolo; Raffo, Luigi Coarse-Grained Reconfiguration: Run-time Adaptivityin Cyber Physical Systems Miscellaneous 2017. @misc{Palumbo2017b, title = {Coarse-Grained Reconfiguration: Run-time Adaptivityin Cyber Physical Systems}, author = {Francesca Palumbo and Carlo Sau and Paolo Meloni and Luigi Raffo}, url = {https://www.cerbero-h2020.eu/wp-content/uploads/2017/09/Sau_SIE2017.pdf}, year = {2017}, date = {2017-06-21}, journal = {SIE 2017}, abstract = {Functional approximate computing methodologies combined with coarse-grained reconfigurable design approached are prospectively suitable to address variable run-time trade-off management typical of evolvable cyber-physical systems. This abstract presents preliminary achievements in HEVC interpolation filters acceleration to be used to trade quality for energy in an ocean monitoring case to be developed in an H2020 project. }, keywords = {}, pubstate = {published}, tppubtype = {misc} } Functional approximate computing methodologies combined with coarse-grained reconfigurable design approached are prospectively suitable to address variable run-time trade-off management typical of evolvable cyber-physical systems. This abstract presents preliminary achievements in HEVC interpolation filters acceleration to be used to trade quality for energy in an ocean monitoring case to be developed in an H2020 project. |
Retweeted by CERBERO
reply
retweet
favorite
© 2017 CERBERO | All Rights Reserved |
Project ID: 732105,
Funded under: H2020-EU.2.1.1. - INDUSTRIAL LEADERSHIP - Leadership in enabling and industrial technologies - Information and Communication Technologies (ICT).