Multigrain reconfiguration

Take a look at the Multigrain Reconfiguration demo

Currently, the hardware adaptivity provided in CERBERO is based on the multi-grain reconfiguration, given by the combination of ARTICo³ framework and MDC tool. This integration delivers the best of both CGR and DPR approaches into an adaptive multi-grain heterogenous reconfigurable fabric, which can meet the changing of functional, non-functional and repair-oriented requirements of CPS designs. The CERBERO approach is not simply meant to provide a novel architecture, rather it aims at offering support the design of the different parts of the system, their deployment and runtime management.

The hardware generation flow starts from high-level dataflow descriptions of the configurations/behaviors to be implemented in the configurable logic, and the integrated toolchain derives the corresponding CGR HDL computational kernel, properly wrapping it with the glue logic necessary to serve as an ARTICo³ DPR reconfigurable partition. Both reconfiguration mechanisms are transparently managed by the user code running in a host processor. With respect to the standalone MDC and ARTICo³ flows, an adaptation step (Kernel Adapter) is needed to make the MDC-generated kernels compliant with kernels expected by ARTICo³ Wrapper Automation step.

The whole MDC-ARTICo³ design flow is as follows.

1. Firstly, MDC merges the user-defined dataflow specifications and generates the CGR computing core.
2. Then, the generated mm-TIL is modified by the Kernel Adapter which delivers an HDL ARTICo³-compliant CGR kernel.
3. Finally, the ARTICo³ framework processes the input HDL CGR kernel to implement the whole reconfigurable processing system.
4. The bottom part of the Figure depicts an example of multi-grain reconfiguration. In this example the CGR approach offered by MDC is exploited for low-power fast-switching of functionality, while the DPR supported by ARTICo³ is exploited for changing the number of slots working in parallel to increase the throughput or provide fault tolerance.